Related: Target Variables as Prerequisites in Makefile
I am trying to create a Makefile that uses a target variable to specify the output directory for object files and the final executable. The idea is to support two separate binary versions, a release version and a debug version with additional debugging information.
My problem is that make makes a clean build every time, even if I haven't changed anything. I am sure that βmakeβ evaluates the prerequisites of the target βcorewarsβ before declaring the variable in the prerequisites for the βdebugβ or βreleaseβ target.
The Makefile is presented below.
CXX=g++
LD=g++
LDFLAGS=
CXXFLAGS=-Iinclude -Wall -Wextra
OBJECTS=main.o Machine.o Core.o ProcessQueue.o Instruction.o
OUTPUT_DIR:=Test/
.PHONY: default
.PHONY: all
.PHONY: release
default: release
all: release
release: OUTPUT_DIR:=Release/
release: corewars
.PHONY: debug
debug: CXXFLAGS+=-DDEBUG -g
debug: OUTPUT_DIR:=Debug/
debug: corewars
corewars: $(OUTPUT_DIR) $(addprefix $(OUTPUT_DIR),$(OBJECTS))
$(LD) -o $(addprefix $(OUTPUT_DIR),corewars) $(addprefix $(OUTPUT_DIR),$(OBJECTS))
Release:
mkdir -p $@
Debug:
mkdir -p $@
%.o: %.cpp include/%.h
$(CXX) -c $(CXXFLAGS) $< -o $(OUTPUT_DIR)$@
.PHONY: clean
clean:
$(RM) -r Release
$(RM) -r Debug