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Is it possible to write type object types in VHDL?

So, I recently inherited some VHDL code, and my first reaction was: "VHDL has structures, why do they use bit vectors everywhere?" And then I realized that this is because there seems to be no way to write something like this:

entity Queue is
    generic (
        EL : type
    );
    port (
        data_in  : EL;
        data_out : EL;
        ...
    );
end entity Queue;

I really wanted it to be possible. Is there anything even remotely approximating this? Even if I need to re-declare entity or component declarations, just somehow somehow avoid re-typing the architecture definition for each type (modulo total width)?

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2 answers

Yes, and queuing is one of the classic reasons to do it!

VHDL VHDL-2008. 2012 . !

  • Aldec .
  • Modelsim - . , /technotes/vhdl 2008.note
  • Xilinx (XST/ISIM) VHDL-2002. , PDF VHDL, VHDL-1993.
  • Altera , generics
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...

- VHDL-2008: http://www.doulos.com/knowhow/vhdl_designers_guide/vhdl_2008/vhdl_200x_major/#GenericTypes

VHDL-2008 EDA - . , .

VHDL-2002, , mytypes , use work.mytypes.all.

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