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Overflow defined for VHDL numeric_std, signed / unsigned

If I have unsigned(MAX downto 0)one containing a value 2**MAX - 1, do the VHDL standards (87 | 93 | 200X) comply, what happens when I increment it by one? (Or, similarly, when I decrease it by one from zero?)

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3 answers

Short answer:

There is no overflow handling, overflow transfer is simply lost. Thus, the result is just the integer result of your work modulo 2 ^ MAX.

Longer answer:

A package numeric_stdis a standard package, but it is not a Core VHDL standard (87.93,200X). For reference: numeric_std.vhd

+ ADD_UNSIGNED (L, R : unsigned; C : std_logic) ( C = '0'). , / unsigned.

:

function ADD_UNSIGNED (L, R : unsigned; C : std_logic) return unsigned is
    constant L_left : integer   := L'length-1;
    alias XL        : unsigned(L_left downto 0) is L;
    alias XR        : unsigned(L_left downto 0) is R;
    variable RESULT : unsigned(L_left downto 0);
    variable CBIT   : std_logic := C;
begin
    for i in 0 to L_left loop
        RESULT(i) := CBIT xor XL(i) xor XR(i);
        CBIT      := (CBIT and XL(i)) or (CBIT and XR(i)) or (XL(i) and XR(i));
    end loop;
    return RESULT;
end ADD_UNSIGNED;

, "" , CBIT='1' ( ) i = L_left. RESULT(i) , .

+6

, unsigned / C, Verilog, (result delta are unsigned):

result <= unsigned(std_logic_vector(resize(('1' & result) - delta, result'length))); -- proper underflow
result <= unsigned(std_logic_vector(resize(('0' & result) + delta, result'length))); -- proper overflow

'0' & result unsigned, 1 , . MSB resize, . underflow.

+1

MAX, 7, 1 2 ** 7 - 1 (127) 2 ** 7 (128).

:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity foo is
end entity;

architecture faa of foo is
    constant  MAX: natural := 7;
    signal somename:  unsigned (MAX downto 0) := (others => '1');
begin
UNLABELED:
    process
    begin
        report "somename'length = " & integer'image(somename'length);
        report "somename maximum value = " &integer'image(to_integer(somename));
        wait;
    end process;
end architecture;

(others => '1') "1" somename, .

:

foo.vhdl: 15: 9: @0ms: ( ): somename'length = 8
foo.vhdl: 16: 9: @0ms: ( ): somename = 255

8, , , 0 2 ** 8 - 1 (255), 2 ** 7 (128), .

This has been seen in the newer issue of the VHDL modulo 2 ^ 32 supplement . In the context of your accepted answer, it is assumed that you meant length instead of the leftmost value.

A decrease from zero of the case leads to the value 2 ** 8 - 1 (255) (MAX = 7). Deficiency or overflow depending on your math religion.

Hat advice to Jonathan Drolet for pointing out a related new question.

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