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How to specify an integer array as shared in VHDL?

I am trying to create a generic driver for an SPI-based I / O expander. The idea is to pass initialization values ​​in an instance that matches the requested I / O setting.

My current attempt looks like this:

entity max7301_simple is
   generic ( 
        IO_cfg : array (1 to 7) OF integer range 0 to 255 := (16#55#, 16#55#, 16#55#, 16#55#, 16#55#, 16#55#, 16#55#)
           );
     port  (
        -- Application interface :
        clk_i       :   in std_logic;        -- input clock, xx MHz.
        rst_i       :   in std_logic;        -- sync reset.
        en_i        :   in std_logic;        -- enable, forces re-init of pins on MAX7301.
        output_i    :   in std_logic_vector(27 downto 0);   --data to write to output pins on MAX7301
        irq_o       :   out std_logic;       -- IRQ, TODO: what triggers, change on inputs ?
        input_o     :   out std_logic_vector(27 downto 0);  --data read from input pins on MAX7301
        -- MAX7301 SPI interface
        sclk        :   out std_logic;        -- SPI clock
        din         :   in std_logic;        -- SPI data input
        dout        :   out std_logic;       -- SPI read data
        cs          :   out std_logic        -- SPI chip select
    );
end max7301_simple;

The problem is with the IO_cfg array, I tried various attempts w / wo init values, etc. And it may not seem like specifying an array.

I believe I read that you can pass the array as a general, but so far it has not been very lucky. Xilinx ISE just reports a “syntax error” next to the “array”, which is not informative enough for me.

Any help would be appreciated

When creating an instance of this module, I always need 7 values.

+5
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3

, , , .

( ), use .

, :

-- package declaration
package mytypes_pkg is

     type my_array_t is array (1 to 7) of integer range 0 to 255;

end package mytypes_pkg;

-- entity "uses" the package   
use work.mytypes_pkg.all;

entity max7301_simple is
   generic ( 
        IO_cfg : my_array_t := (16#55#, 16#55#, 16#55#, 16#55#, 16#55#, 16#55#, 16#55#)
           );
   -- ports [...]
end max7301_simple;

use , .

( )

, ?

VHDL VHDL (2002) , interface_constant_declaration, :

[§ 4.3.2]
interface_constant_declaration ::=  
            [ constant ] identifier_list : [ in ] subtype_indication [ := static_expression ]

[§ 4.2]
subtype_indication ::= 
            [ resolution_function_name ] type_mark [ constraint ]

(type_mark) .

+6

, 2008 VHDL - . :   

package data_types is
    type array_of_integers is array(integer range <>) of integer;
end package;

:   

generic(
    COEFFICIENTS : array_of_integers := (-1, 0, 1)
);

. 'left ( : http://www.csee.umbc.edu/portal/help/VHDL/attribute.html):

-- First coefficient
    ... <= COEFFICIENTS(COEFFICIENTS'left);
-- Second coefficient
    ... <= COEFFICIENTS(COEFFICIENTS'left + 1);

- loop generate:

GENERATE_STATEMENT: for entry in 0 to COEFFICIENTS'length-1 generate
    out(entry) <= std_logic_vector(to_signed(COEFFICIENTS(COEFFICIENTS'left + entry), out(entry)'length));
end generate;

Quartus II .bdf . - A (D "-1", D "0", D "1" ), D ( : http://quartushelp.altera.com/14.0/mergedProjects/assign/asd/asd_tab_param.htm)

+3

If you don't mind a more limited general type, you can do:

generic (IO_cfg : integer_vector);

For now, you have the VHDL-2008 compiler.

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