Geek asks and answers

C ++ 11 atomic x86 memory order

In one of the docs for atomic variables in C ++ 0x, describing the order of memory, he mentions:

Purchase Exemption Order

On highly ordered systems (x86, SPARC, IBM mainframe), the release order is automatic. No additional CPU instructions for this synchronization mode require specific compiler optimizations ...

First, is it true that x86 follows strict memory ordering? It seems very ineffective to always impose it. So, each record and reading has a fence?

Also, if I have a aligned int on an x86 system, do atomic variables serve any purpose whatsoever?

+5
source share
4 answers

, , x86 , . 3A, 8.2 Intel. x86, 386, ( ), x86 , . , Pentium 486 , , (, , ).

, . - .

, x86. , read-modify-write . , ( std::atomic<T> ++ 11), , ; std::atomic, , , x86.

+11

, x86 , .

, ++: , std::atomic.

, , x86 , , /. ( mfence.) ++ , , . , , .

(Pre-++ 11 , , GCC __sync_*, . , , .)

+4

, , () x86 . ( , Alpha) .

, , x86 . .

. , , , . , , . , - .

+1

, release/ . x86 enter image description here, , @Adam Rosenfield Wikipedia. x86 .

Kerrek SB :

, , x86 , , /. ( mfence.)

, ! (. cppreference).

, ...

#include <atomic>
#include <cassert>
#include <string>

std::atomic<std::string*> ptr;

void producer()
{
    std::string* p  = new std::string("Hello");
    ptr = p;
}

void consumer()
{
    std::string* p2;
    while (!(p2 = ptr))
        ;
    assert(*p2 == "Hello"); // never fails
}

(g++ -std = ++ 11 -S -O3 x86)

... mfence x86 (enter image description here).

...

#include <atomic>
#include <cassert>
#include <string>

std::atomic<std::string*> ptr;

void producer()
{
    std::string* p  = new std::string("Hello");
    ptr.store(p, std::memory_order_release);
}

void consumer()
{
    std::string* p2;
    while (!(p2 = ptr.load(std::memory_order_acquire)))
        ;
    assert(*p2 == "Hello"); // never fails
}

(g++ -std = ++ 11 -S -O3 x86)

... no mfence , x86 .

0

More articles:


All Articles