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Mark Verilog Counter

I was wondering how I can write verilog for a tick counter. When fast entry is low, the output tick is high for one cycle every 150 ms (every 7,500,000 cycles). The clk period is 20 ns. If the quick entry is high, the checkmark should go up for one cycle for every measure.

I think I should read the clk loops and use the counter to display the checkmark as high when the number of loops is running, but I can't get it to work.

heres my code:

module tick_counter(
  input  clk,
  input  reset,
  input  fast,
  output reg tick
);

reg count;

always @(posedge clk) begin
  count <= count + 1;
  if((fast == 1)&&(count == 2)) begin
    tick <= 1;
  end
  else if(fast == 0)&&(count == 7500000)) begin
    tick <= 1;
  end
end
endmodule
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2 answers

Your counter has a width of only 1 bit, you did not enable reset, if necessary, you also do not reset the counter. == 2 will be just a phase shift == 7500000. Try:

module tick_counter(
  input  clk,
  input  reset,
  input  fast,
  output reg tick
);

reg [22:0] count;

always @(posedge clk or negedge reset) begin
  if (~reset) begin
    count <= 'd0;
    tick  <=   0;
  end
  else begin
    if((fast == 1)&&(count == 2)) begin
      tick  <= 1;
      count <= 'd0;
    end
    else if(fast == 0)&&(count == 7500000)) begin
      tick  <= 1;
      count <= 'd0;
    end
    else begin
      tick  <= 0;
      count <= count + 1;
    end
  end
end
endmodule

- :

reg  [22:0] count;

wire [22:0] comp = (fast) ? 23'd2: 23'd7500000 ;
wire        done = count >= comp               ;

always @(posedge clk or negedge reset) begin
  if (~reset) begin
    count <= 'd0;
    tick  <=   0;
  end
  else begin
    if(done) begin
      tick  <= 1;
      count <= 'd0;
    end
    else begin
      tick  <= 0;
      count <= count + 1;
    end
  end
end
+4

- - :

module tick_counter(  
  input  wire clk,  
  input  wire resetn,  
  input  wire fast,  
  output reg  tick);  

  reg  [22:0] count;  

  wire [22:0] load = (fast) ? 23'd2: 23'd7500000;  
  wire        done = !count;  

  always @(posedge clk or negedge resetn) begin  
    if (!resetn) begin  
      count <= 23'd0;  
      tick  <= 1'b0;  
    end else begin  
      tick  <= 1'b0;  
      count <= count - 23'd1;  
      if(done) begin  
        tick  <= 1'b1;  
        count <= load;  
      end  
    end  
  end  
endmodule//tick_counter

, , up-counter .

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