Geek asks and answers

Verilog Question Mark Operator (?)

I am trying to translate a Verilog program to VHDL and stumbled upon a statement where the Verilog program uses an operator with a question mark ( ?).

Below is the Verilog code;

1  module music(clk, speaker);
2  input clk;
3  output speaker;
4  parameter clkdivider = 25000000/440/2;

5  reg [23:0] tone;
6  always @(posedge clk) tone <= tone+1;

7  reg [14:0] counter;
8  always @(posedge clk) if(counter==0) counter <= (tone[23] ? clkdivider-1 : clkdivider/2-1); else counter <= counter-1;

9  reg speaker;
10  always @(posedge clk) if(counter==0) speaker <= ~speaker;
11  endmodule

I do not understand the eighth line, can anyone shed light on this? I read on asic-world that the question mark is an alternative to Verilog for the symbol. ZBut I do not understand why this is used in this context.

Yours faithfully

+6
source share
3 answers

This is a ternary operator . This is a shorthand for if statement

Format:

condition ? if true : if false

Example:

tone[23] ? clkdivider-1 : clkdivider/2-1

Translates to something like (not the correct syntax, but I think you will get it):

if tone[23] is 1, counter = clkdivider-1
else counter = clkdivider/2-1

2 1 MUX, if .

- asic-world

+12

, . Verilog:

q <= tone[23] ? clkdivider-1 : clkdivider/2-1;

VHDL :

q <= clkdivider-1 when tone[23] else clkdivider/2-1;
+5

Note that you can bind this operator as follows

q <= <1st condition> ? <1st choice> : <2nd condition> ? <2nd choice> : <3rd choice>

This is a shorthand for priority if .. else if .. else if .. else coding

0
source

More articles:


All Articles