Geek asks and answers

Passing target name based on makefile

If the following rule is in the makefile:

$(OBJ)/%.o: $(SRC)/%.c
    $(CC) -c -o $@ $< $(CFLAGS)

Each file corresponding to the prefix ./obj/and sufix .owill have its own kernel passed in %, so I can provide some dependencies based on its name.

But let's say I have a rule that I specify the target objects one after another that I want:

OBJECTS=abc.o bca.o cba.o
$(OBJECTS): $(SRC)/%.c
    $(CC) -c -o $@ $< $(CFLAGS)

How to make the trunk %actually work for the current name of the target being executed? Just use %does not work, either $@.

Note that I am trying to write the actual target name into my own dependency. For example, when make executes the rule for abc.o, it will include $(SRC)/abc.cjust it (something like $(patsubst %.o, $(SRC)/%.c, MAGIC_TARGET_NAME_VARIABLE)).

+5
2

:

$(OBJECTS): $(SRC)/%.c

:

$(OBJECTS) : %.o : $(SRC)/%.c

$(OBJ) -o , , :

$(OBJECTS) : %.o : $(SRC)/%.c
     $(CC) -c -o $(OBJ)/$@ $< $(CFLAGS)
+11

, , , , :

OBJECTS=abc.o bca.o cba.o

.PHONY: all
all: $(OBJECTS:%=obj/%)

$(OBJ)/%.o: $(SRC)/%.c
    echo $(CC) -c -o $@ $< $(CFLAGS)

.o ; .o .c; .o, ${OBJECTS}.

, , , , , , , .

+1

More articles:


All Articles