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VHDL Alternative Submodule Architecture for Simulation

I have a VHDL component that implements a DRAM test sequence. It contains a child object, which is a DRAM controller.

I want to simulate (debug) a DRAM test sequence, but use a simple fake for a DRAM controller, not the real complicated thing.

Is there a way to set this, possibly using VHDL configurations, to use a simple version of the controller object for simulation? I am completely new to simulation and am not very versed in VHDL in general.

This is the use of Xilinx ISE and ISIM to target Spartan-6, if that matters.

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2 answers

One way that does not use configurations:

, .

Controller_1 : entity work.DRAM_controller(simple)
               port map ( ...


Controller_2 : entity work.DRAM_controller(rtl)
               port map ( ...

"" "rtl" - . , , ; Xilinx (- , !)

DRAM .

vermaete, . - , , , .

, Ashenden ( VHDL ch 5.4, .136 1996 ) DRAM!

EDIT: ( , )

unit test , .

, DRAM UUT ( ) - () DRAM, () DRAM. , - . ENTITY (UUT) .

, , . 2 ; , . . , , .

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generate :

sim:if in_simulation generate
   Controller_1 : entity work.DRAM_controller(simple)
                  port map ...
else
   Controller_1 : entity work.DRAM_controller(rtl)
                  port map ...
end generate;

in_simulation.

( VHDL2008 , if...else..end generate, if in_simulation/if not in_simulation. :)

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