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Synthesis and Simulation Independent Clock Divider

I am new to VHDL while working on homework.

I have a very simple clock divider using common. (This is a counter / separator.)

-- the actual divider will be 2.1e6 or so (25Mhz down to 15hz)
run_divider : clk_divider
--pragma synthesis off
    generic map(clkmax => 4) -- simulation
--pragma synthesis on
    generic map(clkmax => 50000) -- synthesis
      port map( clk_in => mclk,
                reset => rst,
                clk_out => divider_out );

Have I partially used the #ifdef equivalent in VHDL to separate simulation / synthesis? with the above pragma. However, this only works in synthesis, but is a syntax error in the simulation.

Other than using an external tool (M4, C preprocessor as another answer), is there a better way to have separate code for synthesis and modeling? I would like to stop worrying about these constants when I switch between synthesis and simulation.

24MHz 12MHz 8MHz VHDL? , / , : -)

: https://github.com/linuxlizard/vhdl/blob/master/divider.vhdl

!

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3

, generate - - , . , :

constant in_simulation : boolean := false
--synthesis translate_off
                                    or true
--synthesis translate_on
;

:

constant in_simulation : integer  := 0
--synthesis translate_off
                                    + 1
--synthesis translate_on
;

constant in_synthesis : integer  := 1
--synthesis translate_off
                                    - 1
--synthesis translate_on
;

:

constant clkmax_coefficient : integer := 4*in_simulation + 50000*in_synthesis;

run_divider : clk_divider
    generic map(clkmax => clkmax_coefficient)
...
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, , .

- 50000 , :

    -- the actual divider will be 2.1e6 or so (25Mhz down to 15hz)
run_divider : clk_divider
--pragma synthesis off
    generic map(clkmax => 4) -- simulation
--pragma synthesis on
      port map( clk_in => mclk,
                reset => rst,
                clk_out => divider_out );

, clkmax 4, 50000.

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You can use the operator generatein combination with the flag booleanin the package.

g_simulation : if SIMULATION_FLAG generate
    run_divider : clk_divider
    generic map(clkmax => 4) -- simulation
    port map(clk_in => mclk,
        reset => rst,
        clk_out => divider_out);
end generate g_simulation;

g_synthesis : if not SIMULATION_FLAG generate
    run_divider : clk_divider
    generic map(clkmax => 50000) -- synthesis
    port map(clk_in => mclk,
        reset => rst,
        clk_out => divider_out);
end generate g_synthesis;

You may be able to write a simple simulator / synthesis script that installs SIMULATION_FLAGbefore compiling your sources (or just change it manually if you don't need to do this often).

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