Geek asks and answers

How to convert 24MHz and 12MHz clock to 8MHz clock using VHDL?

I am writing code using VHDL to convert a 24 MHz and 12 MHz clock to an 8 MHz clock. Can someone help me with this coding? Thanks in advance.

-1
source share
3 answers

Is it for FPGA? Or something different? Are you really sharing a watch or just a signal? To divide by three counters, try this link:

http://www.asic-world.com/examples/vhdl/divide_by_3.html

And for 2/3:

http://www.edaboard.com/thread42620.html

+1
source

As Martin said, use the Xilinx-recommended sync control device to split your watch to a lower speed.

, .

:

  • . "gotchas", , reset, ..
  • , . . ( S3-A).
  • FPGA Editor, (.. ).
  • .
+1

DCM PLL ( FPGA) - . , , .

EDIT: , Spartan 3ADSP - :

  • , VHDL Verilog , , , , .
  • DCM Userguide DCM /.

reset DCM 0 , . , , , , .

0

More articles:


All Articles