Make call from make file

I have a Makefile that works fine from a new shell, i.e.

make -C /dir/

However, if I invoke this Makefile from another Makefile, it fails due to some complex dependency problems. Clearly familiarize yourself with the nested calls, as evidenced by printing make[1]:, etc., And I suspect that make somehow shares the variables with its child process.

Is there a call to pure makefile from the makefile? If my assembly works from a clean shell, it can be called from another Makefile without resorting to the horrors inside the script! :)

Thank!