A typical way would be to set a high-precision clock (for example, a processor cycle counter) to initiate the interruption of some random and unknown time in the future and to measure the difference in time between the clocks in the ISR compared to the time when the ISR was reached.
(The “random” part of this is to avoid taking measurements systematically during silence or busy times — for example, you don’t want your timer interrupt to systematically trigger at the same time as the network card interrupt, unfairly pushing your latent numbers up.)
The tool that implements this somewhat is Cyclictest , although it seems to measure time inside the kernel thread, not the ISR itself, which will slightly increase your measured delay numbers.