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Verilog 2D Shift

I do not know what does not work on the following code, but it does not synthesize:

reg [7:0] FIFO [0:8];

always@(posedge clk) begin
    if(wr & !rd & !full) begin
       FIFO[0:8] <= {data_in, FIFO[1:8]};
    end
end

I also tried indexing FIFOs in other ways, but nothing works. Found this thread on the Xilinx forum, but I just can't figure out what he wanted to say. Here's the link:

http://forums.xilinx.com/t5/General-Technical-Discussion/2-dimensional-array-problem-in-Verilog/td-p/42368

thank

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2 answers

, . 7.4.1, 7.4.2, 7.4.4 7.4.5 IEEE1800-2012. IEEE1800 SystemVerilog, - Verilog. , , IEEE1800 , IEEE1364.

LRM, - ieee.org: IEEE Std 1800- 2012

. : for-loop, , .

/* Using for-loop */
reg [7:0] FIFO [0:8];
integer i;
always@(posedge clk) begin
    if(wr & !rd & !full) begin
       for(i = 8; i > 0; i=i-i) begin
          FIFO[i] <= FIFO[i-1];
       end
       FIFO[0] <= data_in;
    end
end

/* Using double packed array */
reg [0:8] [7:0] FIFO; // NOTE: format and usage explained in IEEE1800-2012 7.4.5
always@(posedge clk) begin
    if(wr & !rd & !full) begin
       FIFO[0:8] <= {data_in,FIFO[0:7]};
    end
end
+4

. , FIFO (reg [7: 0] FIFO [0: 8]) (reg [7: 0] [0: 8] FIFO).

reg [7:0] FIFO [0:8];

always@(posedge clk) begin
    if(wr & !rd & !full) begin
       FIFO[0] <= data_in;
       FIFO[1:8] <= FIFO[0:7];
    end
end
+1

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