How to run a loop in Verilog?

Do for loops in Verilog run in parallel? I need to call the module several times, but they must be executed at the same time. Instead of writing them one by one, I thought about using a for loop. Will this work the same way?

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Verilog describes hardware, so it makes no sense to think in terms of looping or calling modules in this context. If I understand your question correctly, you would like to have several instances of the same module with different inputs and outputs.

For this, you can use Verilog to generate instructions to automatically create instances.

auto_template nofollow noreferrer > verilog-mode. , , .

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jlf, generate. for-loop , , . .

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