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How to restart Verilog simulation in Modelsim

I am trying to debug a Verilog module. I find it tedious to stop the simulation, change the code, and then start the simulation process again. Is there an easier way?

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It is called restart:-) Simulate โ†’ Run โ†’ Restart

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Here are my one-time liners for simple iterations:

To start a simulation and create a waveform:

vlog your_file.v; vsim work.your_TB; add wave -position insertpoint sim:/your_TB/*;

When updating the code and testing new iterations:

vcom your_file.v; restart -f; run -A;
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ModelSim 'restart' , / testbench , .

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Usually the design has not changed, and you just want to run it against the updated testbench. In this case, you can restart the simulation by executing a custom script that you invoke with the "do {script -name}" command when necessary.

vlog -reportprogress 300 -work work testbench.v
restart -f
run 1us

Assumptions: testbench file = testbench.v; simulation time = 1us

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