Make: setting up target variables with different goals

I am creating a makefile that will be used to create a target or debug target library. I want to put the object and automatically generated dependency files in the structure of the debug or release directory, depending on the requested file target. I don’t want to specify a test command line argument (i.e. DBG = 1), but would rather run make -f Makefile or make -f Makefiel dbg to issue and debug target targets, respectively. Got this part. I understand that I cannot assign a target variable containing the name of the dir object (release or debug), which can be used as part of the Target specification in the rule, as it was in the example shown below. In this example, OBJDIR is the target variable that I would like to set depending on the purpose of the build.For this reason, in this example, $ (OBJDIR) is empty in the target rule $ (OBJDIR) /%. O. Any recommendations on how to complete the proposed steps? (The above example is just an unverified copy / paste example ... the syntax has not been verified ... in fact, I can not display the tabs correctly ... I hope to get some implementation ideas). (Also, $ (OBJDIR) is not set to a pure target, as shown ... because it is not in the dbg / all target hierarchical hierarchy ... thoughts?) Thanks in advance.since it is not in the dbg / all target hierarchical hierarchy ... thoughts?) Thanks in advance.since it is not in the dbg / all target hierarchical hierarchy ... thoughts?) Thanks in advance.

Makefile:

OBJS    := a.o b.o c.o  
SRCS    := $(OBJS:.o=.c)  

-- Set up the release and the debug directory paths and object filenames  
RELEASE_DIR := ./release  
RELEASE_OBJ := $(OBJS:%=$(RELEASE_DIR)/%)  
DEBUG_DIR   := ./debug  
DEBUG_OBJ   := $(OBJS:%=$(DEBUG_DIR)/%)  

.PHONY : all dbg 

all: CFLAGS = -O3  
all: OBJDIR := RELEASE_DIR  
all: df     := $(RELEASE_DIR)/$(*F)  
all: init_release lib1.so  

dbg: CFLAGS = -g -O0  
dbg: OBJDIR := DEBUG_DIR  
dbg: df     := $(DEBUG_DIR)/$(*F)  
dbg: init_debug lib1.so  

Lib1.so: $(OBJ)  

init_release:  
    -@mkdir -p $(RELEASE_DIR)  

init_debug:  
    -@mkdir -p $(DEBUG_DIR)  

lib1.so: $(OBJ)  
    @echo '--------------------------------------------------------------'
    @echo linking $@  
    @gcc -shared -o lib1.so $(OBJ)  

-Compile including advance dependancy generation alg, per Tom Tromey:
    # http://make.paulandlesley.org/autodep.html  
$(OBJDIR)/%.o: %.c  
    echo $@    
    echo $(OBJDIR)  
    echo compiling $@  
    $(COMPILE.c) -MD -o $@ $<  
    cp $(df).d $(df).P; \  
    sed -e 's/#.*//' -e 's/^[^:]*: *//' -e 's/ *\\$$//' \  
             -e '/^$$/ d' -e 's/$$/ :/' < $(df).d >> $(df).P; \  
    rm -f $(df)/$*.d  

# If the goal is "clean", don't include these to avoid trying to build them
ifneq($(MAKECMDGOALS),clean)  
-include $(SRCS:%.c=$(OBJDIR)/%.P)
endif  

clean:  
    -@rm -f    $(OBJDIR)/*.[Pdo] lib1.so  
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2 answers

Target specific variables can be complex. Use indirection instead. Make has a lot of syntax for cutting template text. .SECONDEXPANSIONoften good. Sketch:

.SECONDEXPANSION:
${DEBUG_OBJ} ${RELEASE_OBJ}: $$(patsubst %.o,%.c,$${@F})
    gcc ${copts-${@D}} -c $< -o $@

Here we say that ./release/a.odepends on a.c. When make decides to build ./release/a.o, it expands the shell line. How it does this is ${@D}natural release, therefore make continues and expands ${copts-release}, which you define with benefit.

Similarly, when created, ./debug/a.omake expands ${copts-debug}.

Rapid deployment $(warning [blah]), $(error [blah blah])and mandatory --warn-undefined-variableswill help you get it right.

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Makefile , , . , CFLAGS all dbg.

, , make Makefile, dbg, . :.

ifdef DBG
CFLAGS = -O0 -ggdb
OBJDIR = dbgdir
else
CFLAGS = -O2
OBJDIR = reldir
endif

all: $(OBJDIR)/target
    #Your commands here

dbg:
    $(MAKE) DBG=1

, make, . make dbg, .

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