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MIPS pipelining issue

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Is it necessary to forward (highlighted by a blue arrow)? I realized that the add command successfully writes back to register before the OR instruction reads it.

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addIt is recorded for registration at the same step that it oris read from the register, therefore there is no guarantee that the correct value will be safe in the register at the point orit is seen - addone full clock cycle is allowed to record and transmit signals across all equipment. On the contrary, it xoris safe because it reads from r1 in the next measure after addwrite.

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