can you tell what is the point of this
Are there any possible side effects after using this statement?
This is just a shortcut to listing all the wires the block depends on always. These wires are a "sensitivity list". One of the advantages of using this is that the synthesized code is unlikely to care about what you put on the sensitivity list (except for posedgeand negedge), because the wires will be “physically” connected together. The simulator can rely on a list to select which events should trigger block execution. If you change the block and forget to update the list, your simulation may be at variance with the actual synthesized behavior.
always
posedge
negedge
At SystemVerilog, we would prefer that you use begin_comb begin ... end, rather than always @ *.
@* , - , @* 0, . always_comb 0 .
always_comb , . , , , @* .
@ Ben Jackson answered correctly. The answer to the second part is the absence of side effects; I consider this a recommended practice for combinatorial logic.