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Machine State Encoding in VHDL

I am creating a system in VHDL that filters the image after it is received through the FTDI USB-to-serial device. As part of this, I believe that I determined the states that my CPLD should be in, but I had never created a complex state machine in VHDL before, so I wonder if my methods are sound. Currently, the main circuit for my state machine is:

begin
    process(clk, reset, USB_RXFN, USB_TXEN)
    begin
        case state is
            when IDLE =>
            when NEGOTIATING =>
            when RECEIVING =>
            when FILTERING =>
            when TRANSMITTING =>
            when OTHERS  => -- this should never happen but go to IDLE
    end process;

My problem is that every textbook on a state computer that I could find changes on every front (or similar, but once per cycle), and this device should sit in IDLE a lot and only go to NEGOTIATION when USB_RXFN goes low, stay in the TALK until it ends, stay in RECEIPT until the whole image is transferred, etc.

Is there anything fundamentally wrong with my approach? Are CPLDs simply unsuitable for this purpose? Or is it possible to remain in a state for more than one hour, and the textbooks are simply written for simplicity?

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2 answers

In short, the tutorials you read were just written for simplicity.

- , . VHDL, - State, NextState, - :

architecture foo of bar is
    type StateType is (IDLE, NEGOTIATING, RECEIVING, FILTERING, TRANSMITTING);
    signal State : StateType;
    signal NextState : StateType;
begin
    FSM: process(clk, reset)
    begin
        if reset='1' then
            State <= IDLE;
        elsif clk'event and clk='1' then
            State <= NextState;
        end if;
    end process FSM;

    STATES: process(State, USB_RXFN, USB_TXEN) -- ...
    begin
        NextState <= State; -- by default, stay in the same state (avoid a latch while you're at it)
        case State is
            when IDLE =>
                if USB_RXFN='0' then
                    NextState <= NEGOTIATING;
                end if;
            -- etc
        end case;
    end process STATES;
end foo;
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, / , , . . (TomiJ 2- , - TomiJ), , " ".

architecture foo of bar is
begin
    FSM: process(clk, reset)
        type StateType is (IDLE, NEGOTIATING, RECEIVING, FILTERING, TRANSMITTING);
        variable state, next_state : StateType;
    begin
        if reset='1' then
            state := IDLE;
            next_state := IDLE;
        elsif rising_edge(clk) then
            case state is
                when IDLE =>
                    if USB_RXFN='0' then
                        next_state := NEGOTIATING;
                    end if;
                -- etc
            end case;
            -- Perform other logic based on state or next_state here

            -- finally update state for next time
            state := next_state;
        end if;
    end process FSM;
end foo;
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