Nested if (rising_edge (clk)) in VHDL

so Ive come across some old code that I need to replicate, but it won’t compile with the new Xilinx compiler, so I need to find out exactly what it does. I have something like this:

if rising_edge(clk) then
   —do some things
   if rising_edge(clk) then
      —do some other things
   end if
end if

Does it take 2 clock cycles to go to the internal if statement, or is the second if statement just redundant?

In addition, Xilinx gives an error: "The logic for the signal is clock-driven, but does not seem to be a valid sequential description"

Thanks and any help is appreciated.