VHDL: signals and ports, on which side of the "arrow" =>
very simple question:
How do I know where the port / signal / value should be placed on which side of the arrow? I noticed that by switching
port_a => xto x <= port_a, which seems very equal, I got an error. Also x => port_anot working
I don’t even know in which direction the arrows should point.
The answers are really appreciated!
<=- this is an assignment, in particular an assignment of a signal, controlling a signal with a value from another place. For a physical analogy, a thing on the right side brings value to the left side.
=>- This is a mapping of ports from a pin to a signal. This is not a task - a physical analogy can solder a pin to a wire.
"" , => port map. "" ( , ), x <= port_a port map.
if => for a list of ports, how is this possible? Please note: clk_40Mhz_i is a pin.
COMPONENT clk_wiz_v3_5 is
Port
(- Hours in ports
CLK_IN1: in std_logic;
- Disable ports
CLK_OUT1: out std_logic;
- Status and control signals
RESET: in std_logic;
LOCKED: out std_logic
);
END COMPONENT;
xclk_wiz_v3_5: clk_wiz_v3_5
PORT MAP (
CLK_IN1 => clk_40Mhz_i,
-- Clock out ports
CLK_OUT1 => clk_40Mhz,
-- Status and control signals
RESET => pic_fpga_reset,
LOCKED => clk_locked
);
pic_fpga_reset <= not (processor_fpga_resetn_i);
RESET <= not (clk_locked);