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How to make bitwise AND on integers in VHDL?

I am learning VHDL and I have a problem with the code I'm trying to write in order to satisfy the related validation exception.

Here is my main summary code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_unsigned.all; 
...
port(
Address: in std_logic_vector(15 downto 0);
...
constant SIZE : integer := 4096;
variable addr: integer range 0 to SIZE-1 := 0;
...
process ... 
addr := conv_integer(Address) and (SIZE-1); --error here

The error message I get is

src / memory.vhd: 37: 35: no function declarations for the "and" operator

Basically, my goal is to create a 16-bit address bus, the reference memory is only 4096 bytes. Why am I getting this odd error? Am I missing a library or something else?

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4 answers

First: Do not use std_logic_arithand numeric_std. And you do not needstd_logic_arith

You cannot do bitwise ANDs on integers, so you need to do something like:

addr := Address and to_unsigned(SIZE-1, Address'length);

But you probably want to guarantee that SIZE is power-2

, ​​ :

constant mem_bits : integer := 16;
constant SIZE     : integer := 2**16;


addr := Address(mem_bits-1 downto 0);
+3

, and , , .

std_logic_vector? , , , , .

addr a std_logic_vector(11 downto 0) 12 address, 4 4096 ( 8- ).

+2

. - , , .. .

- ;

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;





entity testand is
    generic (nBITS:integer:=32);
    port (
        i:in integer;
        a:in std_logic_vector(nBITS-1 downto 0);
        o:out std_logic_vector(nBITS-1 downto 0));
end entity;



architecture beh of testand is

signal v:std_logic_vector(a'length-1 downto 0);

begin

    v<=std_logic_vector(conv_unsigned(i,o'length));

    o<=v and a;


end architecture;
+2

In your particular case, you can also use the "SIZE mod" instead of "and (SIZE-1)".

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