I am looking for some examples of implementing a hash table (insert + search) in Verilog (VHDL will work too). My case is not very complicated, because I know all the values during initialization, so I can pretty much say how much memory I need, find out its boundaries, etc. The hash function is not complicated, and I have an idea on how to map the hash key with memory addresses, manage collisions, etc. But to write all this for the first time from scratch is a resource, and there may be errors that I don’t know about. This will help if I can use some kind of link design. Therefore, if you know about such a thing, please share. Both fees / payment are ok, I could buy an IP implementation of this if it comes with source code that I can use to study.
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