module A (
output A_OPORT_1
);
endmodule
module B (
input B_IPORT_1
);
endmodule
module TestBench;
wire A_to_B;
A A_inst (
.A_OPORT_1 (A_to_B)
);
B B_inst (
.B_IPORT_1 (A_to_B)
);
endmodule
Here basically the output port A: A_inst: A_OPORT_1 is connected to B: B_inst: B_IPORT_1
How can I get this information using PLI verilog? An example is being evaluated.
I have a code that receives a port and retrieves highconn and can receive A_to_B wire / network.
However, I cannot find out which ports are connected to A_To_B using vpiPortInst. I get an iterator that is null.
vpiHandle high = vpi_handle(vpiHighConn, port);
vpi_printf(" High conndata type is %s\n",
vpi_get_str(vpiType, high));
vpi_printf(" High conndata Net type is %s\n",
vpi_get_str(vpiNetType, high));
vpi_printf(" High conndata Name is %s\n",
vpi_get_str(vpiFullName, high));
vpiHandle iter = vpi_iterate(vpiPortInst,high);
vpiHandle p2ref;
if (iter == NULL)
{
vpi_printf(" Port Iterator is null\n");
}
O / P:
High conndata type is vpiNet
High conndata Net type is vpiWire
High conndata Name is $unit::A_to_B
Port Iterator is null
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