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Unknown error Verilog "pending" endmodule "

In verilog, I have an error that I cannot go through. this is the first bit of code and then the last bit

 module Decoder(op,funct,aluop,mwr,mreg,mrd,alusrc,regdst,regwr,btype);
  input[5:0] op,funct;
  output[2:0] aluop;
  output[1:0] btype;
  output mwr,mreg,mrd,alusrc,regdst,regwr;
  wire aluop,mwr,mreg,mrd,alusrc,regdst,regwr,btype;
  case(op)
      6'b000000: begin
          case(funct)
              6'b001010:
                  assign aluop = 3'b010;
              6'b001100:
                  assign aluop = 3'b111;
              6'b010001:
                  assign aluop = 3'b011;
              default:
                  assign aluop = 3'b000;          
          endcase
          assign btype = 2'b00;
          assign mwr = 1'b0;
          assign mreg = 1'b0;
          assign mrd = 1'b0;
          assign alusrc = 1'b0;
          assign regdst = 1'b1;
          assign regwr = 1'b1;
          end

...

  default: begin
      assign aluop = 3'b000;
        assign mwr = 0;
        assign mreg = 0;
        assign mrd = 0;
        assign alusrc = 0;
        assign btype = 2'b00;
        assign regdst = 0;
        assign regwr = 0;
        end
endcase

endmodule

he continues to give me the following errors

Error (10170): Verilog HDL syntax error on Decoder.v (7) near the text "case"; waiting for "endmodule" Error (10170): Verilog HDL syntax error in Decoder.v (14) next to the text "6"; waiting for "endmodule"

It also does this at each end of the instruction and by default and endcase

I have no idea why this is being done; I'm pretty new to verilog.

early

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2 answers

, case if/else always. , , , , .

:

//change wire types to reg type

always @*
begin
  case (op)
    6'b000000: begin
      aluop = 3'b000
    end
    ...
  endcase
end
+6

, , , , , IEEE 1364-2001 verilog . , Tim - , , , .

, , Verilog "" . , , . reg/wire, , , .

module mod;

reg reg1;           //Module item
wire wire1;         //Module item
assign wire1 = 0;   //Module item
always reg1 = 0;    //Module item
parameter con1 = 0; //Module item
 //Instances a different module based on con1
case(con1)          //Module item
  0:mod2 inst1(reg1);
  1:mod3 inst1(reg1);
  2:mod4 inst1(reg1);
endcase

endmodule

-, , . , , , .

module mod2;
reg a;

always
  begin
  a = 0; //Procedural statement
  end

initial
   a = 0; //Procedural statement 

function func1(input arg1);
case (arg1) //Procedural statement 
  0:func1 = 0; 
  default:func1 = 9;
endcase
endfunction

endmodule

2001 Verilog case, case-. , , . case . , case .

verilog, 1364-2005, , 2001 generate..endgenerate. IEEE 1364-2001, , , .

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