Geek asks and answers

Debug combinational logic loops in Icarus Verilog

I use Verilog Icarus to model a fairly complex design. I found that in some rare cases my simulation is "stuck", i.e. The clock no longer goes out, and none of the signals change. I suspect this is due to the fact that I have a combinational logic loop somewhere in my design. The problem, of course, is that I have no idea where.

Is there a systematic method for debugging this? I'm just really tired of the code, but I can't make any progress. Any suggestions that I can try are greatly appreciated.

+3
source share
3 answers

When you run the simulation, upload the VCD file. If you have an infinite loop, you will see that the size of the VCD file continues to grow without new time being written to the file. Times are indicated by the symbol #at the beginning of the line. You will be able to determine which signals change without time.

+3
source

So, Icarus Verilog has a compilation flag "-pfileline = 1" for this particular one. Running vvp with the flag turned on prints all the debugging information about what is being done.

+1
source

IMO, . , . , :

`timescale 1ns / 1ns
 real period;
 reg clk;

 initial begin
     period = 5.0;
     clk = 1'b0;
     forever begin
         #(period/2) clk = !clk;
     end
end

period, , period 0.0.

, period / 2 . , period = 1.0, period / 2 0,5, 1ns, 0, . , , ( , ...).

...
half_period_ns = period_ns / 2.0; 
if( half_period_ns == 0 )
    half_period_ns = 1;
#(half_period_ns) clk = !clk;
...

- Ctrl-C, , , ( , , Incisive it where, ), . , , .

0

More articles:


All Articles