GNU make: a list of object files from a list of sources taken from a mapped variable

So I have a variable:

PROGS = element0 \
        element1

I have variables for each of them:

element0_SRCS = src/xxx.c src/q.c
element1_SRCS = src/xxx.c src/z.c

If I have a different set of variables, I can do what I want quite easily:

element0_OBJS = src/xxx.o src/q.o
element1_OBJS = src/xxx.o src/z.o

ALL_PROGS = $(foreach p, $(PROGS), $(p)_prog)
all : $(ALL_PROGS)

.SECONDEXPANSION:
%_prog : $$($$*_OBJS)
     gcc - blah blah

However, I want to eliminate the need for "_OBJS" vars and use _SRCS. I can do this person with each program:

element0_prog : $(element0_SRCS:.c=.o)

Various attempts to use the second extension to recreate the% _prog rule, however, have failed.

$$($$*_SRCS:.c=.o) ==> target template does not contain '%'

$$(patsubst %.c,%.o,$$($$*_SRCS)) ==> creates a target with .c files instead of .o files.

Largely at a loss here.

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1 answer

Use static pattern :

prog_objs = $($*_SRCS:.c=.o)

.SECONDEXPANSION:
$(ALL_PROGS) : %_prog : $$(prog_objs)
    gcc - blah blah
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