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Armv8 - AArch64 vs AArch32 Register stack pointer?

Background: In AArch32, each mode (FIQ, IRQ, etc.) has a “bank” copy of the SP register (R13). This allowed various modes to maintain their own separate stack.

Now on AArch64, this does not seem to be the case. For example: if we consider EL1, then on AArch64 two modes equivalent to IRQ and SVC are equal to EL1h and EL1t (h = handler and t = stream). In this case, should the "h" and "t" modes use a common stack? I ask because on EL there is only one stack pointer, namely SP_ELx.

Questions:

  • How AArch64 manages this difference for OSs like Linux. Would two modes, like EL1h and EL1t, use the same stack?
  • Similar to AArch32, where Linux has different stacks for IRQ and SVC modes, what would you need to do to support different stacks for EL1'h 'and EL1't', in the case of AArch64?
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First of all, we need to separate ARMv7 / ARMv8 (architecture versions) from the run states of AArch32 / AArch64 (32-bit or 64-bit).

If the ARMv8 processor provides AArch32 execution status on EL1 (the kernel), it has the same exception model as in ARMv7. When EL1 is in AArch64 runtime, it uses a completely different exception handling model.

AArch64 EL1 does not have IRQ and SVC or other modes that AArch32 does - that is why it needs / has only one exception stack.

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