Connecting ports by name in VHDL, UCF-style

I have a VHDL object defined as follows:

entity RealEntity is
  port(
    CLK_50MHZ: in std_logic;
    LED : out std_logic_vector(3 downto 0)
    );
end RealEntity;

If I also have UCF entries for LED<0>..LED<3>and CLK_50MHZ, I can compile this object directly.

However, I actually don't have a 50 MHz clock, so I have to use a timer chip. I use the Xilinx tools for this, which has a wizard to add the DCM core, and then I move it to another VHDL object for ease of use:

entity dcm is
  port(
    CLK_32MHZ: in std_logic;
    CLK_50MHZ: out std_logic
    );
end dcm;

where CLK_32MHZis what really exists in my UCF.

To connect the two, I am currently using a third object, which will be used as my top level:

entity main is
  port(
    CLK_32MHZ : in  std_logic;
    LED       : out std_logic_vector(3 downto 0)
    );
end main;

architecture arch of main is
  signal CLK_50MHZ : std_logic;

  component dcm
    port(
      CLK_32MHZ : in  std_logic;
      CLK_50MHZ : out std_logic
      );
  end component;

  component RealEntity
    port(CLK_50MHZ : in  std_logic;
         LED       : out std_logic_vector(3 downto 0)
         );
  end component;

begin
  inst_dcm : dcm
    port map(
      CLK_32MHZ => CLK_32MHZ,
      CLK_50MHZ => CLK_50MHZ
      );

  inst_RealEntity : RealEntity
    port map(
      CLK_50MHZ => CLK_50MHZ,
      LED       => LED
      );

end arch;

, 100% - . : main, RealEntity dcm , CLK_50MHZ, , CLK_50MHZ UCF?