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Limitations for arrays in the system verilog

Is it possible to use the initially generated random elements to limit the sequential elements of a randomized array. For example: I want to generate a set of 10 pairs of addr, size, to simulate a typical memory allocation procedure and have a class like this:

class abc;
  rand bit[5:0] size[8];
  rand bit[5:0] addr[8];

  constraint mem_unique{
  foreach(size[i]) begin
    solve size[i] before addr[i];
    size[i] inside {[6'h2:6'h10]};
    if(i>0)
      addr[i] > addr[i-1]+size[i-1];
  end
  }
endclass:abc
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2 answers

A few extra lines of code in your example would show if it works or not. Here is what I should work:

module top;
class abc;
   rand bit[5:0] size[8];
   rand bit[6:0] addr[8];

   constraint mem_unique
     {
      foreach(size[i]) {
                       size[i] inside {[6'h2:6'h10]};
                       if(i>0) // concatenate 1'b0 to catch overflow
                          {1'b0,addr[i]} > addr[i-1]+size[i-1];
                       }
     }
endclass : abc
   abc c=new();
   initial repeat(5) begin
      $display();
      assert(c.randomize());
      foreach(c.addr[i]) $displayh(c.addr[i],, c.size[i]);
   end
endmodule  top

The foreach constraint expands, as does the synthesis tool. So you are left with something like:

 size[0] inside {[6'h2:6'h10]};
 size[1] inside {[6'h2:6'h10]};
 {1'b0,addr[1]} > addr[0]+size[0];
 size[2] inside {[6'h2:6'h10]};
 {1'b0,addr[2]} > addr[1]+size[1];
 ...

 size[7] inside {[6'h2:6'h10]};
 {1'b0,addr[7]} > addr[6]+size[6];
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, , , , , - . , , , , -. post_randomize:

class abc;
  rand bit[5:0] size[10];
  rand bit[5:0] offset[10];
  bit[5:0] addr[10];

  constraint mem_unique{
    foreach(size[i]) size[i] inside {[6'h10:6'h20]};
    (size.sum + offset.sum) <= 6'h3F;
  }

  function void post_randomize();
    foreach(addr[i]) begin
      if(i == 0) addr[i] = offset[i];
      else addr[i] = addr[i-1] + size[i-1] + offset[i];
    end
  endfunction

endclass

, , , 6'h10 ('d16), 10 . , 0, 'd160 (' hA0). addr .

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